Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods for fabricating high performance finFET devices using epitaxial layer with over-growth suppression.
Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure.
FinFET designs use “fins” that may be formed on the surface of a semiconductor wafer using selective-etching processes. The fins may be used to form a raised channel between the gate and the source and drain of a transistor. The gate is then deposited such that it wraps around the fin to form a trigate structure. Since the channel is extremely thin, the gate would generally have a greater control over the carriers within. However, when the transistor is switched on, the shape of the channel may limit the current flow. Therefore, multiple fins may be used in parallel to provide greater current flow for increased drive strength.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art FinFET device. A FinFET device 100 illustrated in FIG. 1 comprises a plurality of “fins” 110. The semiconductor device may be position to a vertical orientation, creating one or more fins 110. The source and drain of the FinFET are placed horizontally along the fin. A high-k metal gate 120 wraps over the fin, covering it on three sides. The gate 120 defines the length of the FinFET device. The current flow occurs along an orthogonal crystal plane in a direction parallel to the plane of the semiconductor wafer. The electrically significant height of the fin (labeled H) is typically determined by the amount of oxide recess in the fin reveal step and hence is constant for all fins 110.
The thickness of the fin (labeled Tfi) determines the short channel behavior of the transistor device and is usually small in comparison with the height H of the fin 110. The pitch (labeled P) of the fins is determined by lithographic constraints and dictates the wafer area to implement the desired device width. A small value of the pitch P and a large value of the height H enable a better packing of the devices per square area resulting in a denser design, or more efficient use of silicon wafer area.
The scaling down of integrated circuits coupled with higher performance requirements for these circuits have prompted an increased interest in finFETs. FinFETs generally have the increased channel widths, which includes channel portions formed on the sidewalls and top portions of the fins. Since drive currents of the finFETs are proportional to the channel widths, finFETs generally display increase drive current capabilities.
Typically, in order to increase performance capability of devices, designers had proposed increasing the height of the fins in state of the art finFETs. Increasing the height of the fins would increases would increase the current drive of the finFET, thereby increasing performance of the finFETs. However, the greater height would cause the device to be larger in size, leading to larger sized integrated circuit made from the finFETs.
Another state of the art solution offered by designers includes growing an epitaxial (EPI) layer at the top of source/drain fins of finFETs. FIG. 2 illustrates a stylized depiction of a cross-sectional view of a typical growth of EIP layer at the top of source/drain fins of a typical finFET. A plurality of fins 220a, 220b, 220c are formed in a shallow trench isolation (STI) layer 210 for manufacturing finFETs 200.
To increase the current drive of the finFETs 200, the source-drain fins 220, epitaxial (EPI) layers 230 are formed on the fins 220. One problem associated with the state of the art includes the fact that as the EIP layers 230 are formed on the fins 220, lateral growth may cause a short to occur between fins 210b and 210c, which are fins of different finFET devices. Although the connection of the EPI layer 230 between fins 220a and 220b are not problematic since they belong to the same device, the short between the EPI layer between the fins 220b and 220c are problematic since they are respectively of different devices. Therefore, this process is not possible in many designs, such as designs that contain tight chip design rules and densely arranged devices and/or fins. Some designers have attempted to suppress lateral EPI growth to address this problem. However, this approach limits the EPI layers in such a manner that high leakage currents may be induced because contact silicide can be formed too close to the channel.
FIG. 3 illustrates a stylized depiction of a top view layout of a typical finFET device. FIG. 3 illustrates two gate regions 310a, 310b of a finFET device 300. FIG. 3 shows source-drain fins 320. EPI growth 330 may be formed at the top of the fins 320 to enhance current drive. However, as shown in the portion above the gate 310b, a source-drain bridge 350 may occur due to the over-growth of the EPI layer 330, causing a short upon the end of the gate 310b. This short may cause various errors and operational problems.
The present disclosure may address and/or at least reduce one or more of the problems identified above.